Salvatore Monteleone

Presentation - a Research Assistant in Computer Engineering at the University of Catania, Italy where he received his Ph.D. degree in Communications and Computer Engineering in 2014.

He has published 1 book chapter, 6 refereed international journals and 23 conference papers.

He is Chair of the Technical Program Committee of NoCArc workshop (held in conjunction with MICRO) and member of the Technical Program Committee of the conferences:

- ICCEA, International Conference on Computer Engineering and Application,

- CTRQ, International Conference on Communication Theory, Reliability, and Quality of Service

- ScalCom, International Conference on Scalable Computing and Communications,

- NetACT, International Conference on Networks and Advances in Computational Technologies.

Dr. Monteleone is an affiliated member of the European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC). He is a member of IEEE and of the IEEE Internet of Things and IEEE Sustainable ICT Communities.

His general research area is embedded systems design & applications with contributions mainly focused on low-power design, Network-on-Chip architectures, and IoT based systems.

Research project -

The role played by the on-chip communication system, based on the Network-on-Chip (NoC) paradigm, is becoming more and more important as the number of processing elements increases. Wireless NoC (WiNoC) architectures are considered nowadays as the most viable solution for addressing the scalability limitations of future manycore architectures. Unfortunately, there is a lack of tools and methodologies for optimizing WiNoC based architectures in a multi-objective fashion. Main issues are due to the lack of simulation environments and estimation models to rapidly assess a WiNoC configuration. The main goal of the proposed collaboration, entitled "Design Methodologies for Energy Efficient Emerging NoC Architectures (E3NoC)" is the design and implementation of a framework aimed at exploring the wide design space spanned by the architectural and micro-architectural parameters of WiNoC based architectures. The optimization process will also involve the optimization of the application to be mapped by means of the Approximate Computing paradigm. Another important point of this collaboration is to share the know-how especially for what concerns the study of power consumption modeling of several parts of the RF-NoC communication chain including the digital part implemented on FPGAs. Other expected outcomes and benefits will include the chance for scientific publications and the basis for a common research project proposal that would include exchange students programs as happened in the past.


  • Seminar : January 28, 2020
    “The Network-on-Chip paradigm: Challenges and Opportunities”