Energy consumption in reconfigurable systems

Thematic day in the framework of the "Risks, Society and Security" (R2S) thematic cycle

The objective of this thematic day is to bring together the academic and industrial communities working on energy consumption in reconfigurable systems (FPGA, FPAA) and to lay out the state of the art in new technologies, tools, and platforms available for designing energy-efficient systems. An assessment of the existing platforms dedicated to energy consumption will be performed in order to share information on the various initiatives that exist at the national level

Date: December 6, 2017
LocationMaison Internationale de la Recherche
Public: Open to anyone interested in the "Risks and Security" theme
Registration is closed

Presentation of the subject

Over the last years, embedded systems have developed greatly to provide high performance as well as improved autonomy and energy efficiency. Their increasing complexity has often resulted in solutions with poor energy efficiency. Today, reconfigurable systems (FPGA, FPAA) look like a solution adapted to the rapid development of low-cost complex flexible systems However, energy consumption remains a major bottleneck in many application fields such as telecommunications, security, health, internet of things, etc. It is therefore necessary to imagine new strategies in order to better take into account energy issues early in the design process.

There are two objectives for this thematic day: bringing together the academic and industrial worlds (researchers and students) in order to exchange on energy consumption in reconfigurable systems and lay out the state of the art in new technologies, tools, and platforms available to design energy-efficient systems.

Program

9.00 – 10.00: Registration - Coffee
10.00 – 10.15: Opening of the day's proceedings
10.15 – 10.45: Presentation 1: "5G: are we going to deliver what we promised?", Mérouane Debbah – University Professor at Central-Supelec, Vice-President of Huawei France R&D.
10.50 – 11.20: Presentation 2: "Energy use optimization techniques for FPGA – Xilinx circuits", Ludovic Aubel, Strategic Applications Engineer, Xilinx.
11.25 – 11.55: Presentation 3: "Power Consumption Analysis and Hardware Security", A. Tisserand - CNRS Research Director at the Lab-STICC.
12.00 – 1.30: Cocktail lunch
1.30 - 2.00: Presentation 4: "Open People Platform", Eric Senn, Associate Professor - HDR - Lab-STICC, University of Bretagne Sud.
2.05 – 2.35: Presentation 5: "FoRTReSS: a flow for design space exploration of partially reconfigurable systems", S. Bilavarn, Associate Professor - LEAT - University of Nice Sophia Antipolis.
2.40 – 3.10: Presentation 6: "ViPar : Design space exploration for parallel reconfigurable architectures", Rabie Ben Atitallah, University Professor - LAMIH - University of Valenciennes.
3.15 – 3.30: Coffee break
3.30 – 4.00: Poster Session
4.00 – 4.30: Round table and discussion
4.30 – 5.00: Conclusion and wrap-up

More information about the presentations

For any information, contact the organizer:  Jordane Lorandel (jordane.lorandel @ u-cergy.fr), Associate Professor, Paris-Seine University, University of Cergy-Pontoise, ENSEA, UMR 8051 CNRS, ETIS Laboratoire – ASTRE team
UCP laboratories involved in the organization of this conference: ETIS
Funders:
the University of Cergy-Pontoise Institute of Advanced Studies